From 5d793b13c5701ee7d2ba49d788aad437bf20c60a Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Povi=C5=A1er?= Date: Tue, 6 Jan 2026 22:32:43 +0100 Subject: [PATCH 1/5] synth: Enable verilog compat if all files are .v MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit When using slang in synthesis, switch on Verilog compatibility if all source file names end in `.v` Signed-off-by: Martin Povišer --- flow/scripts/synth_preamble.tcl | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/flow/scripts/synth_preamble.tcl b/flow/scripts/synth_preamble.tcl index d8f98c8f69..f1775f80e8 100644 --- a/flow/scripts/synth_preamble.tcl +++ b/flow/scripts/synth_preamble.tcl @@ -75,6 +75,17 @@ proc read_design_sources { } { # Add user arguments lappend slang_args {*}$::env(SYNTH_SLANG_ARGS) + # If the sources are solely .v files, enable Verilog compatibility + set has_non_v_files false + foreach fn $::env(VERILOG_FILES) { + if { [file extension [string trim $fn]] != ".v" } { + set has_non_v_files true + } + } + if { !$has_non_v_files } { + lappend slang_args --std=1364-2005 + } + yosys read_slang {*}$slang_args # Workaround for yosys-slang#119 From d7caef0dddab652123cfd6f66f187ce130806d7c Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Povi=C5=A1er?= Date: Tue, 6 Jan 2026 23:21:58 +0100 Subject: [PATCH 2/5] synth: Pass `--ignore-timing` to slang MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Pass the extra flag to make slang ignore a class of synthesizable language features. Signed-off-by: Martin Povišer --- flow/scripts/synth_preamble.tcl | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/flow/scripts/synth_preamble.tcl b/flow/scripts/synth_preamble.tcl index f1775f80e8..fc109ab1d2 100644 --- a/flow/scripts/synth_preamble.tcl +++ b/flow/scripts/synth_preamble.tcl @@ -47,7 +47,8 @@ proc read_design_sources { } { plugin -i slang set slang_args [list \ - -D SYNTHESIS --keep-hierarchy --compat=vcs --ignore-assertions --top $::env(DESIGN_NAME) \ + -D SYNTHESIS --keep-hierarchy --compat=vcs --ignore-assertions \ + --ignore-timing --top $::env(DESIGN_NAME) \ {*}$vIdirsArgs {*}[env_var_or_empty VERILOG_DEFINES]] # slang requires all files at once From 977f1fb710355242f979454bfd069d38199c5231 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Povi=C5=A1er?= Date: Wed, 7 Jan 2026 12:18:57 +0100 Subject: [PATCH 3/5] synth: Make "slang" the default frontend MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Make slang the default and apply a number of opt-outs across the design suite. The opt-outs are for designs which don't go through with slang today, usually because the input is not fully up to spec. Private designs which weren't using slang previously get an opt-out to save on private CI churn. Signed-off-by: Martin Povišer --- docs/user/FlowVariables.md | 2 +- flow/designs/asap7/aes/config.mk | 2 ++ flow/designs/asap7/ethmac/config.mk | 2 ++ flow/designs/asap7/ethmac_lvt/config.mk | 2 ++ flow/designs/asap7/mock-cpu/config.mk | 2 ++ flow/designs/asap7/riscv32i/config.mk | 2 ++ flow/designs/asap7/swerv_wrapper/config.mk | 2 ++ flow/designs/gf12/aes/config.mk | 1 + flow/designs/gf12/ariane/config.mk | 1 + flow/designs/gf12/ariane133/config.mk | 1 + flow/designs/gf12/bp_dual/config.mk | 1 + flow/designs/gf12/bp_quad/config.mk | 1 + flow/designs/gf12/bp_single/config.mk | 1 + flow/designs/gf12/coyote/config.mk | 2 ++ flow/designs/gf12/gcd/config.mk | 2 +- flow/designs/gf12/ibex/config.mk | 1 + flow/designs/gf12/jpeg/config.mk | 2 +- flow/designs/gf12/swerv_wrapper/config.mk | 1 + flow/designs/gf12/tinyRocket/config.mk | 2 ++ flow/designs/nangate45/ariane136/config.mk | 2 ++ flow/designs/nangate45/black_parrot/config.mk | 2 ++ flow/designs/nangate45/bp_multi_top/config.mk | 2 ++ flow/designs/nangate45/swerv/config.mk | 1 + flow/designs/nangate45/swerv_wrapper/config.mk | 2 ++ flow/designs/rapidus2hp/ethmac/config.mk | 1 + flow/designs/rapidus2hp/gcd/config.mk | 1 + flow/designs/rapidus2hp/jpeg/config.mk | 1 + flow/designs/sky130hd/chameleon/config.mk | 2 +- flow/designs/sky130hd/microwatt/config.mk | 2 ++ flow/scripts/synth_preamble.tcl | 5 ++++- flow/scripts/variables.yaml | 10 +++++++--- 31 files changed, 53 insertions(+), 8 deletions(-) diff --git a/docs/user/FlowVariables.md b/docs/user/FlowVariables.md index 841c12d07e..a8f108765d 100644 --- a/docs/user/FlowVariables.md +++ b/docs/user/FlowVariables.md @@ -244,7 +244,7 @@ configuration file. | SYNTH_BLACKBOXES| List of cells treated as a black box by Yosys. With Bazel, this can be used to run synthesis in parallel for the large modules of the design.| | | SYNTH_CANONICALIZE_TCL| Specifies a Tcl script with commands to run as part of the synth canonicalize step.| | | SYNTH_GUT| Load design and remove all internal logic before doing synthesis. This is useful when creating a mock .lef abstract that has a smaller area than the amount of logic would allow. bazel-orfs uses this to mock SRAMs, for instance.| 0| -| SYNTH_HDL_FRONTEND| Select an alternative language frontend to ingest the design. Available option is "slang". If the variable is empty, design is read with the Yosys read_verilog command.| | +| SYNTH_HDL_FRONTEND| Select the language frontend to use for ingesting the design. Available options are: "slang" - SystemVerilog input by means of [slang](https://github.com/MikePopoloski/slang) and [yosys-slang](https://github.com/povik/yosys-slang) "yosys" - Verilog and limited SystemVerilog input by means of [internal Yosys support]](https://yosyshq.readthedocs.io/projects/yosys/en/0.40/cmd/read_verilog.html) "verific" - SystemVerilog input via a proprietary extension| slang| | SYNTH_HIERARCHICAL| Enable to Synthesis hierarchically, otherwise considered flat synthesis.| 0| | SYNTH_HIER_SEPARATOR| Separator used for the synthesis flatten stage.| .| | SYNTH_KEEP_MOCKED_MEMORIES| When `SYNTH_MOCK_LARGE_MEMORIES=1`, setting this to 1, will keep mocked memories (not flattening them). This preserves some of the access logic complexity and avoids optimizations outside of the mocked memory.| 1| diff --git a/flow/designs/asap7/aes/config.mk b/flow/designs/asap7/aes/config.mk index a8cb544a32..db3d529d9b 100644 --- a/flow/designs/asap7/aes/config.mk +++ b/flow/designs/asap7/aes/config.mk @@ -29,3 +29,5 @@ else ifeq ($(FLOW_VARIANT),combine) $(WORK_HOME)/results/$(PLATFORM)/$(DESIGN_NICKNAME)/blackbox/1_synth.v \ $(WORK_HOME)/results/$(PLATFORM)/$(DESIGN_NICKNAME)/blackbox/1_synth.v endif + +export SYNTH_HDL_FRONTEND = yosys \ No newline at end of file diff --git a/flow/designs/asap7/ethmac/config.mk b/flow/designs/asap7/ethmac/config.mk index c7770d7137..85e4ec86f9 100644 --- a/flow/designs/asap7/ethmac/config.mk +++ b/flow/designs/asap7/ethmac/config.mk @@ -10,3 +10,5 @@ export CORE_UTILIZATION = 70 export CORE_ASPECT_RATIO = 1 export CORE_MARGIN = 2 export PLACE_DENSITY = 0.75 + +export SYNTH_HDL_FRONTEND = yosys diff --git a/flow/designs/asap7/ethmac_lvt/config.mk b/flow/designs/asap7/ethmac_lvt/config.mk index ff4d402a11..b784e527e2 100644 --- a/flow/designs/asap7/ethmac_lvt/config.mk +++ b/flow/designs/asap7/ethmac_lvt/config.mk @@ -15,3 +15,5 @@ export PLACE_DENSITY = 0.60 export ASAP7_USE_VT = LVT export RECOVER_POWER = 1 + +export SYNTH_HDL_FRONTEND = yosys diff --git a/flow/designs/asap7/mock-cpu/config.mk b/flow/designs/asap7/mock-cpu/config.mk index 2eb0c35ac2..d4da1466f1 100644 --- a/flow/designs/asap7/mock-cpu/config.mk +++ b/flow/designs/asap7/mock-cpu/config.mk @@ -13,3 +13,5 @@ export PLACE_DENSITY = 0.71 export TNS_END_PERCENT = 100 export IO_CONSTRAINTS = designs/asap7/mock-cpu/io.tcl + +export SYNTH_HDL_FRONTEND = yosys diff --git a/flow/designs/asap7/riscv32i/config.mk b/flow/designs/asap7/riscv32i/config.mk index 60313250f5..9eec7cfb08 100644 --- a/flow/designs/asap7/riscv32i/config.mk +++ b/flow/designs/asap7/riscv32i/config.mk @@ -26,3 +26,5 @@ export TNS_END_PERCENT = 100 export CTS_CLUSTER_SIZE = 10 export CTS_CLUSTER_DIAMETER = 50 + +export SYNTH_HDL_FRONTEND = yosys diff --git a/flow/designs/asap7/swerv_wrapper/config.mk b/flow/designs/asap7/swerv_wrapper/config.mk index 2a22c2dde9..1f4dd9e748 100644 --- a/flow/designs/asap7/swerv_wrapper/config.mk +++ b/flow/designs/asap7/swerv_wrapper/config.mk @@ -58,3 +58,5 @@ export IO_CONSTRAINTS = $(DESIGN_HOME)/$(PLATFORM)/swerv_wrapper/io.tcl export PLACE_DENSITY_LB_ADDON = 0.20 export ROUTING_LAYER_ADJUSTMENT = 0.2 + +export SYNTH_HDL_FRONTEND = yosys diff --git a/flow/designs/gf12/aes/config.mk b/flow/designs/gf12/aes/config.mk index 7145449318..672e50c173 100644 --- a/flow/designs/gf12/aes/config.mk +++ b/flow/designs/gf12/aes/config.mk @@ -18,3 +18,4 @@ else export DESIGN_TYPE = CELL_NODEN endif +export SYNTH_HDL_FRONTEND = yosys diff --git a/flow/designs/gf12/ariane/config.mk b/flow/designs/gf12/ariane/config.mk index 28194633ef..768470ca9e 100644 --- a/flow/designs/gf12/ariane/config.mk +++ b/flow/designs/gf12/ariane/config.mk @@ -34,3 +34,4 @@ export DESIGN_TYPE = CELL_NODEN endif export REMOVE_ABC_BUFFERS = 1 +export SYNTH_HDL_FRONTEND = yosys diff --git a/flow/designs/gf12/ariane133/config.mk b/flow/designs/gf12/ariane133/config.mk index 28c9649cd7..0107993961 100644 --- a/flow/designs/gf12/ariane133/config.mk +++ b/flow/designs/gf12/ariane133/config.mk @@ -31,3 +31,4 @@ export DESIGN_TYPE = CELL_NODEN endif export REMOVE_ABC_BUFFERS = 1 +export SYNTH_HDL_FRONTEND = yosys diff --git a/flow/designs/gf12/bp_dual/config.mk b/flow/designs/gf12/bp_dual/config.mk index 3f3e20af00..a57f8b7e59 100644 --- a/flow/designs/gf12/bp_dual/config.mk +++ b/flow/designs/gf12/bp_dual/config.mk @@ -66,3 +66,4 @@ export MACRO_WRAPPERS = $(PLATFORM_DIR)/bp/wrappers/wrappers.tcl export PDN_TCL = $(PLATFORM_DIR)/cfg/pdn_grid_strategy_13m_9T.top.tcl export MACRO_PLACE_HALO = 7 7 +export SYNTH_HDL_FRONTEND = yosys diff --git a/flow/designs/gf12/bp_quad/config.mk b/flow/designs/gf12/bp_quad/config.mk index 5846c209b3..16c66c0f61 100644 --- a/flow/designs/gf12/bp_quad/config.mk +++ b/flow/designs/gf12/bp_quad/config.mk @@ -68,3 +68,4 @@ export MACRO_WRAPPERS = $(PLATFORM_DIR)/bp/wrappers/wrappers.tcl export PDN_TCL = $(PLATFORM_DIR)/cfg/pdn_grid_strategy_13m_9T.top.tcl export MACRO_PLACE_HALO = 7 7 +export SYNTH_HDL_FRONTEND = yosys diff --git a/flow/designs/gf12/bp_single/config.mk b/flow/designs/gf12/bp_single/config.mk index 4748ede574..d9ce1e2a56 100644 --- a/flow/designs/gf12/bp_single/config.mk +++ b/flow/designs/gf12/bp_single/config.mk @@ -68,3 +68,4 @@ endif # enable slack margin for setup and hold fix after CTS export SETUP_SLACK_MARGIN ?= 100 +export SYNTH_HDL_FRONTEND = yosys diff --git a/flow/designs/gf12/coyote/config.mk b/flow/designs/gf12/coyote/config.mk index c801e198ec..9b3215030e 100644 --- a/flow/designs/gf12/coyote/config.mk +++ b/flow/designs/gf12/coyote/config.mk @@ -36,3 +36,5 @@ export DESIGN_TYPE = CELL else export DESIGN_TYPE = CELL_NODEN endif + +export SYNTH_HDL_FRONTEND = yosys diff --git a/flow/designs/gf12/gcd/config.mk b/flow/designs/gf12/gcd/config.mk index 470e63993d..76b9e2ce3b 100644 --- a/flow/designs/gf12/gcd/config.mk +++ b/flow/designs/gf12/gcd/config.mk @@ -18,4 +18,4 @@ export DESIGN_TYPE = CELL_NODEN endif export SKIP_GATE_CLONING = 1 - +export SYNTH_HDL_FRONTEND = yosys diff --git a/flow/designs/gf12/ibex/config.mk b/flow/designs/gf12/ibex/config.mk index 78f928de7f..2a62c37445 100644 --- a/flow/designs/gf12/ibex/config.mk +++ b/flow/designs/gf12/ibex/config.mk @@ -27,3 +27,4 @@ endif # slack margin to address WC corner export SETUP_SLACK_MARGIN ?= 180 export HOLD_SLACK_MARGIN ?= 50 +export SYNTH_HDL_FRONTEND = yosys diff --git a/flow/designs/gf12/jpeg/config.mk b/flow/designs/gf12/jpeg/config.mk index 3a817b948a..06df73b8d7 100644 --- a/flow/designs/gf12/jpeg/config.mk +++ b/flow/designs/gf12/jpeg/config.mk @@ -22,4 +22,4 @@ endif #export SKIP_PIN_SWAP = 1 export SKIP_GATE_CLONING = 1 - +export SYNTH_HDL_FRONTEND = yosys diff --git a/flow/designs/gf12/swerv_wrapper/config.mk b/flow/designs/gf12/swerv_wrapper/config.mk index 2ed5601613..48e0b91ccf 100644 --- a/flow/designs/gf12/swerv_wrapper/config.mk +++ b/flow/designs/gf12/swerv_wrapper/config.mk @@ -37,3 +37,4 @@ export DESIGN_TYPE = CELL_NODEN endif export REMOVE_ABC_BUFFERS = 1 +export SYNTH_HDL_FRONTEND = yosys diff --git a/flow/designs/gf12/tinyRocket/config.mk b/flow/designs/gf12/tinyRocket/config.mk index fe6b436ab9..87f5a98ff1 100644 --- a/flow/designs/gf12/tinyRocket/config.mk +++ b/flow/designs/gf12/tinyRocket/config.mk @@ -38,3 +38,5 @@ export DESIGN_TYPE = CELL else export DESIGN_TYPE = CELL_NODEN endif + +export SYNTH_HDL_FRONTEND = yosys diff --git a/flow/designs/nangate45/ariane136/config.mk b/flow/designs/nangate45/ariane136/config.mk index 04da1dc265..a3514491c6 100644 --- a/flow/designs/nangate45/ariane136/config.mk +++ b/flow/designs/nangate45/ariane136/config.mk @@ -22,3 +22,5 @@ export MACRO_PLACE_HALO = 10 10 export TNS_END_PERCENT = 100 export PLACE_DENSITY = 0.35 + +export SYNTH_HDL_FRONTEND = yosys diff --git a/flow/designs/nangate45/black_parrot/config.mk b/flow/designs/nangate45/black_parrot/config.mk index 771ea51da1..81570558e5 100644 --- a/flow/designs/nangate45/black_parrot/config.mk +++ b/flow/designs/nangate45/black_parrot/config.mk @@ -38,3 +38,5 @@ export MACRO_PLACE_HALO = 10 10 export TNS_END_PERCENT = 100 export HOLD_SLACK_MARGIN = 0.03 + +export SYNTH_HDL_FRONTEND = yosys diff --git a/flow/designs/nangate45/bp_multi_top/config.mk b/flow/designs/nangate45/bp_multi_top/config.mk index e05d37d2e5..5db60204da 100644 --- a/flow/designs/nangate45/bp_multi_top/config.mk +++ b/flow/designs/nangate45/bp_multi_top/config.mk @@ -32,3 +32,5 @@ export MACRO_PLACE_HALO = 10 10 export PLACE_DENSITY_LB_ADDON = 0.05 export SKIP_GATE_CLONING = 1 + +export SYNTH_HDL_FRONTEND = yosys diff --git a/flow/designs/nangate45/swerv/config.mk b/flow/designs/nangate45/swerv/config.mk index 6625aced49..53d4261347 100644 --- a/flow/designs/nangate45/swerv/config.mk +++ b/flow/designs/nangate45/swerv/config.mk @@ -11,3 +11,4 @@ export CORE_MARGIN = 5 export PLACE_DENSITY_LB_ADDON = 0.25 export TNS_END_PERCENT = 100 +export SYNTH_HDL_FRONTEND = yosys diff --git a/flow/designs/nangate45/swerv_wrapper/config.mk b/flow/designs/nangate45/swerv_wrapper/config.mk index 2ce3c88234..0de519e9ab 100644 --- a/flow/designs/nangate45/swerv_wrapper/config.mk +++ b/flow/designs/nangate45/swerv_wrapper/config.mk @@ -23,3 +23,5 @@ export PLACE_DENSITY_LB_ADDON = 0.08 export TNS_END_PERCENT = 100 export FASTROUTE_TCL = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NAME)/fastroute.tcl + +export SYNTH_HDL_FRONTEND = yosys diff --git a/flow/designs/rapidus2hp/ethmac/config.mk b/flow/designs/rapidus2hp/ethmac/config.mk index cd2139c796..b70c106f84 100644 --- a/flow/designs/rapidus2hp/ethmac/config.mk +++ b/flow/designs/rapidus2hp/ethmac/config.mk @@ -25,3 +25,4 @@ export CORE_UTILIZATION = $(strip \ export CORE_ASPECT_RATIO = 1 export CORE_MARGIN = 0.75 export PLACE_DENSITY = 0.70 +export SYNTH_HDL_FRONTEND = yosys diff --git a/flow/designs/rapidus2hp/gcd/config.mk b/flow/designs/rapidus2hp/gcd/config.mk index 5e24cd8d7c..684660f014 100644 --- a/flow/designs/rapidus2hp/gcd/config.mk +++ b/flow/designs/rapidus2hp/gcd/config.mk @@ -30,3 +30,4 @@ export CORE_UTILIZATION = $(strip $(if $(filter 0.15,$(RAPIDUS_PDK_VERSION)), \ export CORE_MARGIN = .5 export PLACE_DENSITY = 0.42 +export SYNTH_HDL_FRONTEND = yosys diff --git a/flow/designs/rapidus2hp/jpeg/config.mk b/flow/designs/rapidus2hp/jpeg/config.mk index 5fc80731f6..9c0e9c267c 100644 --- a/flow/designs/rapidus2hp/jpeg/config.mk +++ b/flow/designs/rapidus2hp/jpeg/config.mk @@ -36,3 +36,4 @@ export CORE_MARGIN = 0.75 export PLACE_DENSITY = 0.62 export TNS_END_PERCENT = 100 +export SYNTH_HDL_FRONTEND = yosys diff --git a/flow/designs/sky130hd/chameleon/config.mk b/flow/designs/sky130hd/chameleon/config.mk index cf331a908f..c72bb9562e 100644 --- a/flow/designs/sky130hd/chameleon/config.mk +++ b/flow/designs/sky130hd/chameleon/config.mk @@ -50,4 +50,4 @@ export FP_PDN_RAIL_WIDTH = 0.48 export FP_PDN_RAIL_OFFSET = 0 export TNS_END_PERCENT = 100 - +export SYNTH_HDL_FRONTEND = yosys diff --git a/flow/designs/sky130hd/microwatt/config.mk b/flow/designs/sky130hd/microwatt/config.mk index 5365b178e6..2b4f0548fa 100644 --- a/flow/designs/sky130hd/microwatt/config.mk +++ b/flow/designs/sky130hd/microwatt/config.mk @@ -48,3 +48,5 @@ ifeq ($(SYNTH_MOCK_LARGE_MEMORIES),1) else export SYNTH_MEMORY_MAX_BITS ?= 42000 endif + +export SYNTH_HDL_FRONTEND = yosys diff --git a/flow/scripts/synth_preamble.tcl b/flow/scripts/synth_preamble.tcl index fc109ab1d2..be6d584425 100644 --- a/flow/scripts/synth_preamble.tcl +++ b/flow/scripts/synth_preamble.tcl @@ -109,7 +109,10 @@ proc read_design_sources { } { if { [env_var_exists_and_non_empty SYNTH_BLACKBOXES] } { error "Non-empty SYNTH_BLACKBOXES unsupported with HDL frontend \"verific\"" } - } elseif { ![env_var_exists_and_non_empty SYNTH_HDL_FRONTEND] } { + } elseif { + [env_var_equals SYNTH_HDL_FRONTEND yosys] || + ![env_var_exists_and_non_empty SYNTH_HDL_FRONTEND] + } { verilog_defaults -push if { [env_var_exists_and_non_empty VERILOG_DEFINES] } { verilog_defaults -add {*}$::env(VERILOG_DEFINES) diff --git a/flow/scripts/variables.yaml b/flow/scripts/variables.yaml index bc6a6188f1..6e569cd4a7 100644 --- a/flow/scripts/variables.yaml +++ b/flow/scripts/variables.yaml @@ -240,11 +240,15 @@ SYNTH_KEEP_MOCKED_MEMORIES: - synth SYNTH_HDL_FRONTEND: description: > - Select an alternative language frontend to ingest the design. Available option - is "slang". If the variable is empty, design is read with the Yosys read_verilog - command. + Select the language frontend to use for ingesting the design. Available options + are: + + "slang" - SystemVerilog input by means of [slang](https://github.com/MikePopoloski/slang) and [yosys-slang](https://github.com/povik/yosys-slang) + "yosys" - Verilog and limited SystemVerilog input by means of [internal Yosys support]](https://yosyshq.readthedocs.io/projects/yosys/en/0.40/cmd/read_verilog.html) + "verific" - SystemVerilog input via a proprietary extension stages: - synth + default: "slang" SYNTH_SLANG_ARGS: description: > Additional arguments passed to the slang frontend during synthesis. From 56d4fd45ecdc4b5f85e3f0588776e9fc30a7803e Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Povi=C5=A1er?= Date: Thu, 8 Jan 2026 21:11:46 +0100 Subject: [PATCH 4/5] synth: Disable slang for nangate45/ariane133 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Martin Povišer --- flow/designs/nangate45/ariane133/config.mk | 2 ++ 1 file changed, 2 insertions(+) diff --git a/flow/designs/nangate45/ariane133/config.mk b/flow/designs/nangate45/ariane133/config.mk index 7e2d41bd63..68eff2efe2 100644 --- a/flow/designs/nangate45/ariane133/config.mk +++ b/flow/designs/nangate45/ariane133/config.mk @@ -27,3 +27,5 @@ export RTLMP_MAX_MACRO = 10 export RTLMP_MIN_MACRO = 1 export RTLMP_MAX_INST = 80000 export RTLMP_MIN_INST = 8000 + +export SYNTH_HDL_FRONTEND = yosys From c19d20c7d10103e0fb6d2df52505739cbcc5ccc2 Mon Sep 17 00:00:00 2001 From: "github-actions[bot]" Date: Tue, 13 Jan 2026 11:25:46 +0000 Subject: [PATCH 5/5] flow: update rules Signed-off-by: github-actions[bot] --- flow/designs/asap7/aes-block/rules-base.json | 4 ++-- flow/designs/asap7/aes-mbff/rules-base.json | 10 +++++----- flow/designs/asap7/gcd-ccs/rules-base.json | 4 ++-- flow/designs/asap7/gcd/rules-base.json | 6 +++--- flow/designs/gf180/aes-hybrid/rules-base.json | 6 +++--- flow/designs/gf180/aes/rules-base.json | 6 +++--- flow/designs/gf180/uart-blocks/rules-base.json | 4 ++-- .../ihp-sg13g2/i2c-gpio-expander/rules-base.json | 4 ++-- flow/designs/nangate45/bp_be_top/rules-base.json | 6 +++--- flow/designs/nangate45/bp_fe_top/rules-base.json | 4 ++-- flow/designs/nangate45/gcd/rules-base.json | 2 +- flow/designs/nangate45/jpeg/rules-base.json | 2 +- flow/designs/nangate45/tinyRocket/rules-base.json | 6 +++--- flow/designs/sky130hd/gcd/rules-base.json | 2 +- flow/designs/sky130hd/jpeg/rules-base.json | 2 +- flow/designs/sky130hd/riscv32i/rules-base.json | 2 +- flow/designs/sky130hs/aes/rules-base.json | 6 +++--- flow/designs/sky130hs/gcd/rules-base.json | 6 +++--- 18 files changed, 41 insertions(+), 41 deletions(-) diff --git a/flow/designs/asap7/aes-block/rules-base.json b/flow/designs/asap7/aes-block/rules-base.json index 22a5a5797c..98699416bb 100644 --- a/flow/designs/asap7/aes-block/rules-base.json +++ b/flow/designs/asap7/aes-block/rules-base.json @@ -12,7 +12,7 @@ "compare": "<=" }, "placeopt__design__instance__count__stdcell": { - "value": 10573, + "value": 19934, "compare": "<=" }, "detailedplace__design__violations": { @@ -64,7 +64,7 @@ "compare": ">=" }, "detailedroute__route__wirelength": { - "value": 52923, + "value": 77305, "compare": "<=" }, "detailedroute__route__drc_errors": { diff --git a/flow/designs/asap7/aes-mbff/rules-base.json b/flow/designs/asap7/aes-mbff/rules-base.json index e3db438ed7..3dc497b2ef 100644 --- a/flow/designs/asap7/aes-mbff/rules-base.json +++ b/flow/designs/asap7/aes-mbff/rules-base.json @@ -28,11 +28,11 @@ "compare": "<=" }, "cts__timing__setup__ws": { - "value": -38.2, + "value": -69.5, "compare": ">=" }, "cts__timing__setup__tns": { - "value": -687.0, + "value": -1500.0, "compare": ">=" }, "cts__timing__hold__ws": { @@ -48,11 +48,11 @@ "compare": "<=" }, "globalroute__timing__setup__ws": { - "value": -49.6, + "value": -72.6, "compare": ">=" }, "globalroute__timing__setup__tns": { - "value": -2160.0, + "value": -3090.0, "compare": ">=" }, "globalroute__timing__hold__ws": { @@ -84,7 +84,7 @@ "compare": ">=" }, "finish__timing__setup__tns": { - "value": -1130.0, + "value": -1500.0, "compare": ">=" }, "finish__timing__hold__ws": { diff --git a/flow/designs/asap7/gcd-ccs/rules-base.json b/flow/designs/asap7/gcd-ccs/rules-base.json index 102e04c4e8..8acbf18d16 100644 --- a/flow/designs/asap7/gcd-ccs/rules-base.json +++ b/flow/designs/asap7/gcd-ccs/rules-base.json @@ -32,7 +32,7 @@ "compare": ">=" }, "cts__timing__setup__tns": { - "value": -103.0, + "value": -207.0, "compare": ">=" }, "cts__timing__hold__ws": { @@ -52,7 +52,7 @@ "compare": ">=" }, "globalroute__timing__setup__tns": { - "value": -102.0, + "value": -187.0, "compare": ">=" }, "globalroute__timing__hold__ws": { diff --git a/flow/designs/asap7/gcd/rules-base.json b/flow/designs/asap7/gcd/rules-base.json index 77f6e8a8d1..87636aea8e 100644 --- a/flow/designs/asap7/gcd/rules-base.json +++ b/flow/designs/asap7/gcd/rules-base.json @@ -32,7 +32,7 @@ "compare": ">=" }, "cts__timing__setup__tns": { - "value": -281.0, + "value": -422.0, "compare": ">=" }, "cts__timing__hold__ws": { @@ -52,7 +52,7 @@ "compare": ">=" }, "globalroute__timing__setup__tns": { - "value": -439.0, + "value": -513.0, "compare": ">=" }, "globalroute__timing__hold__ws": { @@ -84,7 +84,7 @@ "compare": ">=" }, "finish__timing__setup__tns": { - "value": -270.0, + "value": -361.0, "compare": ">=" }, "finish__timing__hold__ws": { diff --git a/flow/designs/gf180/aes-hybrid/rules-base.json b/flow/designs/gf180/aes-hybrid/rules-base.json index 6aa28e58ef..ded043ff05 100644 --- a/flow/designs/gf180/aes-hybrid/rules-base.json +++ b/flow/designs/gf180/aes-hybrid/rules-base.json @@ -32,7 +32,7 @@ "compare": ">=" }, "cts__timing__setup__tns": { - "value": -144.0, + "value": -208.0, "compare": ">=" }, "cts__timing__hold__ws": { @@ -52,7 +52,7 @@ "compare": ">=" }, "globalroute__timing__setup__tns": { - "value": -158.0, + "value": -230.0, "compare": ">=" }, "globalroute__timing__hold__ws": { @@ -84,7 +84,7 @@ "compare": ">=" }, "finish__timing__setup__tns": { - "value": -154.0, + "value": -221.0, "compare": ">=" }, "finish__timing__hold__ws": { diff --git a/flow/designs/gf180/aes/rules-base.json b/flow/designs/gf180/aes/rules-base.json index 75ea8f2a34..5f3492a000 100644 --- a/flow/designs/gf180/aes/rules-base.json +++ b/flow/designs/gf180/aes/rules-base.json @@ -32,7 +32,7 @@ "compare": ">=" }, "cts__timing__setup__tns": { - "value": -107.0, + "value": -141.0, "compare": ">=" }, "cts__timing__hold__ws": { @@ -52,7 +52,7 @@ "compare": ">=" }, "globalroute__timing__setup__tns": { - "value": -124.0, + "value": -165.0, "compare": ">=" }, "globalroute__timing__hold__ws": { @@ -84,7 +84,7 @@ "compare": ">=" }, "finish__timing__setup__tns": { - "value": -119.0, + "value": -157.0, "compare": ">=" }, "finish__timing__hold__ws": { diff --git a/flow/designs/gf180/uart-blocks/rules-base.json b/flow/designs/gf180/uart-blocks/rules-base.json index 550f2f7174..c5fbb3cee7 100644 --- a/flow/designs/gf180/uart-blocks/rules-base.json +++ b/flow/designs/gf180/uart-blocks/rules-base.json @@ -12,7 +12,7 @@ "compare": "<=" }, "placeopt__design__instance__count__stdcell": { - "value": 726, + "value": 1036, "compare": "<=" }, "detailedplace__design__violations": { @@ -64,7 +64,7 @@ "compare": ">=" }, "detailedroute__route__wirelength": { - "value": 18889, + "value": 29243, "compare": "<=" }, "detailedroute__route__drc_errors": { diff --git a/flow/designs/ihp-sg13g2/i2c-gpio-expander/rules-base.json b/flow/designs/ihp-sg13g2/i2c-gpio-expander/rules-base.json index a17e94afaa..b229c7e221 100644 --- a/flow/designs/ihp-sg13g2/i2c-gpio-expander/rules-base.json +++ b/flow/designs/ihp-sg13g2/i2c-gpio-expander/rules-base.json @@ -12,7 +12,7 @@ "compare": "<=" }, "placeopt__design__instance__count__stdcell": { - "value": 951, + "value": 1448, "compare": "<=" }, "detailedplace__design__violations": { @@ -64,7 +64,7 @@ "compare": ">=" }, "detailedroute__route__wirelength": { - "value": 38152, + "value": 46152, "compare": "<=" }, "detailedroute__route__drc_errors": { diff --git a/flow/designs/nangate45/bp_be_top/rules-base.json b/flow/designs/nangate45/bp_be_top/rules-base.json index 92bada3a7b..519e19f31a 100644 --- a/flow/designs/nangate45/bp_be_top/rules-base.json +++ b/flow/designs/nangate45/bp_be_top/rules-base.json @@ -32,7 +32,7 @@ "compare": ">=" }, "cts__timing__setup__tns": { - "value": -12.8, + "value": -16.3, "compare": ">=" }, "cts__timing__hold__ws": { @@ -52,7 +52,7 @@ "compare": ">=" }, "globalroute__timing__setup__tns": { - "value": -18.6, + "value": -19.9, "compare": ">=" }, "globalroute__timing__hold__ws": { @@ -84,7 +84,7 @@ "compare": ">=" }, "finish__timing__setup__tns": { - "value": -17.1, + "value": -19.6, "compare": ">=" }, "finish__timing__hold__ws": { diff --git a/flow/designs/nangate45/bp_fe_top/rules-base.json b/flow/designs/nangate45/bp_fe_top/rules-base.json index fa8424d1d1..9091dc700d 100644 --- a/flow/designs/nangate45/bp_fe_top/rules-base.json +++ b/flow/designs/nangate45/bp_fe_top/rules-base.json @@ -52,7 +52,7 @@ "compare": ">=" }, "globalroute__timing__setup__tns": { - "value": -0.36, + "value": -0.753, "compare": ">=" }, "globalroute__timing__hold__ws": { @@ -84,7 +84,7 @@ "compare": ">=" }, "finish__timing__setup__tns": { - "value": -0.795, + "value": -1.89, "compare": ">=" }, "finish__timing__hold__ws": { diff --git a/flow/designs/nangate45/gcd/rules-base.json b/flow/designs/nangate45/gcd/rules-base.json index 3be227edcb..514c9e0c5f 100644 --- a/flow/designs/nangate45/gcd/rules-base.json +++ b/flow/designs/nangate45/gcd/rules-base.json @@ -64,7 +64,7 @@ "compare": ">=" }, "detailedroute__route__wirelength": { - "value": 4515, + "value": 5793, "compare": "<=" }, "detailedroute__route__drc_errors": { diff --git a/flow/designs/nangate45/jpeg/rules-base.json b/flow/designs/nangate45/jpeg/rules-base.json index 9560dcdda5..d11187344d 100644 --- a/flow/designs/nangate45/jpeg/rules-base.json +++ b/flow/designs/nangate45/jpeg/rules-base.json @@ -84,7 +84,7 @@ "compare": ">=" }, "finish__timing__setup__tns": { - "value": -41.1, + "value": -41.6, "compare": ">=" }, "finish__timing__hold__ws": { diff --git a/flow/designs/nangate45/tinyRocket/rules-base.json b/flow/designs/nangate45/tinyRocket/rules-base.json index 4a1f0fae64..971600da73 100644 --- a/flow/designs/nangate45/tinyRocket/rules-base.json +++ b/flow/designs/nangate45/tinyRocket/rules-base.json @@ -32,7 +32,7 @@ "compare": ">=" }, "cts__timing__setup__tns": { - "value": -23.6, + "value": -58.0, "compare": ">=" }, "cts__timing__hold__ws": { @@ -52,7 +52,7 @@ "compare": ">=" }, "globalroute__timing__setup__tns": { - "value": -39.6, + "value": -70.7, "compare": ">=" }, "globalroute__timing__hold__ws": { @@ -84,7 +84,7 @@ "compare": ">=" }, "finish__timing__setup__tns": { - "value": -33.7, + "value": -69.2, "compare": ">=" }, "finish__timing__hold__ws": { diff --git a/flow/designs/sky130hd/gcd/rules-base.json b/flow/designs/sky130hd/gcd/rules-base.json index b7aced2aee..b5716ec86d 100644 --- a/flow/designs/sky130hd/gcd/rules-base.json +++ b/flow/designs/sky130hd/gcd/rules-base.json @@ -64,7 +64,7 @@ "compare": ">=" }, "detailedroute__route__wirelength": { - "value": 8444, + "value": 10996, "compare": "<=" }, "detailedroute__route__drc_errors": { diff --git a/flow/designs/sky130hd/jpeg/rules-base.json b/flow/designs/sky130hd/jpeg/rules-base.json index f71c0d3e70..a0f1298e90 100644 --- a/flow/designs/sky130hd/jpeg/rules-base.json +++ b/flow/designs/sky130hd/jpeg/rules-base.json @@ -52,7 +52,7 @@ "compare": ">=" }, "globalroute__timing__setup__tns": { - "value": -8.68, + "value": -22.2, "compare": ">=" }, "globalroute__timing__hold__ws": { diff --git a/flow/designs/sky130hd/riscv32i/rules-base.json b/flow/designs/sky130hd/riscv32i/rules-base.json index bc784630ed..41aa713d65 100644 --- a/flow/designs/sky130hd/riscv32i/rules-base.json +++ b/flow/designs/sky130hd/riscv32i/rules-base.json @@ -84,7 +84,7 @@ "compare": ">=" }, "finish__timing__setup__tns": { - "value": -8.38, + "value": -10.1, "compare": ">=" }, "finish__timing__hold__ws": { diff --git a/flow/designs/sky130hs/aes/rules-base.json b/flow/designs/sky130hs/aes/rules-base.json index d3e6d07315..bb1ae9f199 100644 --- a/flow/designs/sky130hs/aes/rules-base.json +++ b/flow/designs/sky130hs/aes/rules-base.json @@ -48,11 +48,11 @@ "compare": "<=" }, "globalroute__timing__setup__ws": { - "value": -0.244, + "value": -0.397, "compare": ">=" }, "globalroute__timing__setup__tns": { - "value": -2.47, + "value": -5.1, "compare": ">=" }, "globalroute__timing__hold__ws": { @@ -84,7 +84,7 @@ "compare": ">=" }, "finish__timing__setup__tns": { - "value": -0.632, + "value": -1.7, "compare": ">=" }, "finish__timing__hold__ws": { diff --git a/flow/designs/sky130hs/gcd/rules-base.json b/flow/designs/sky130hs/gcd/rules-base.json index 4a60b077ca..3122a2c09a 100644 --- a/flow/designs/sky130hs/gcd/rules-base.json +++ b/flow/designs/sky130hs/gcd/rules-base.json @@ -32,7 +32,7 @@ "compare": ">=" }, "cts__timing__setup__tns": { - "value": -10.5, + "value": -11.2, "compare": ">=" }, "cts__timing__hold__ws": { @@ -52,7 +52,7 @@ "compare": ">=" }, "globalroute__timing__setup__tns": { - "value": -16.3, + "value": -16.7, "compare": ">=" }, "globalroute__timing__hold__ws": { @@ -84,7 +84,7 @@ "compare": ">=" }, "finish__timing__setup__tns": { - "value": -12.0, + "value": -12.7, "compare": ">=" }, "finish__timing__hold__ws": {