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Merged
pelwell merged 9 commits into from
Nov 29, 2024
Merged

RP1 clocks #6459

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b448e46
dt-bindings: net: cdns,macb: Add compatible for Raspberry Pi RP1
6by9 Nov 11, 2024
7502d70
net: macb: Add support for Raspberry Pi RP1 ethernet controller
6by9 Nov 11, 2024
944f616
rp1: clk: Only set PLL_SEC_RST in rp1_pll_divider_off
6by9 Nov 25, 2024
4a9e687
rp1: clk: Rationalise the use of the CLK_IS_CRITICAL flag
6by9 Nov 8, 2024
325a73a
dt: arm64: Fixup RP1 ethernet DT configuration
6by9 Nov 11, 2024
95642ab
clk: rp1: Add RP1_CLK_DMA.
6by9 Nov 13, 2024
31993fd
rp1: clk: Remove CLK_IGNORE_UNUSED flags
6by9 Nov 8, 2024
2ade928
dt: rp1: Use clk_sys for ethernet hclk and pclk
6by9 Nov 11, 2024
56a949d
dt: rp1: Link RP1 DMA to the associated clock
6by9 Nov 13, 2024
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1 change: 1 addition & 0 deletions Documentation/devicetree/bindings/net/cdns,macb.yaml
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Original file line number Diff line number Diff line change
Expand Up @@ -54,6 +54,7 @@ properties:
- cdns,np4-macb # NP4 SoC devices
- microchip,sama7g5-emac # Microchip SAMA7G5 ethernet interface
- microchip,sama7g5-gem # Microchip SAMA7G5 gigabit ethernet interface
- raspberrypi,rp1-gem # Raspberry Pi RP1 gigabit ethernet interface
- sifive,fu540-c000-gem # SiFive FU540-C000 SoC
- cdns,emac # Generic
- cdns,gem # Generic
Expand Down
25 changes: 9 additions & 16 deletions arch/arm64/boot/dts/broadcom/rp1.dtsi
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Original file line number Diff line number Diff line change
Expand Up @@ -32,6 +32,7 @@
// RP1_PLL_VIDEO_CORE and dividers are now managed by VEC,DPI drivers
<&rp1_clocks RP1_PLL_SYS>,
<&rp1_clocks RP1_PLL_SYS_SEC>,
<&rp1_clocks RP1_CLK_ETH>,
<&rp1_clocks RP1_PLL_AUDIO>,
<&rp1_clocks RP1_PLL_AUDIO_SEC>,
<&rp1_clocks RP1_CLK_SYS>,
Expand All @@ -46,6 +47,7 @@
<1536000000>, // RP1_PLL_AUDIO_CORE
<200000000>, // RP1_PLL_SYS
<125000000>, // RP1_PLL_SYS_SEC
<125000000>, // RP1_CLK_ETH
<61440000>, // RP1_PLL_AUDIO
<192000000>, // RP1_PLL_AUDIO_SEC
<200000000>, // RP1_CLK_SYS
Expand Down Expand Up @@ -976,12 +978,15 @@

rp1_eth: ethernet@100000 {
reg = <0xc0 0x40100000 0x0 0x4000>;
compatible = "cdns,macb";
compatible = "raspberrypi,rp1-gem", "cdns,macb";
#address-cells = <1>;
#size-cells = <0>;
interrupts = <RP1_INT_ETH IRQ_TYPE_LEVEL_HIGH>;
clocks = <&macb_pclk &macb_hclk &rp1_clocks RP1_CLK_ETH_TSU>;
clock-names = "pclk", "hclk", "tsu_clk";
clocks = <&rp1_clocks RP1_CLK_SYS
&rp1_clocks RP1_CLK_SYS
&rp1_clocks RP1_CLK_ETH_TSU
&rp1_clocks RP1_CLK_ETH>;
clock-names = "pclk", "hclk", "tsu_clk", "tx_clk";
phy-mode = "rgmii-id";
cdns,aw2w-max-pipe = /bits/ 8 <8>;
cdns,ar2r-max-pipe = /bits/ 8 <8>;
Expand Down Expand Up @@ -1076,7 +1081,7 @@
reg = <0xc0 0x40188000 0x0 0x1000>;
compatible = "snps,axi-dma-1.01a";
interrupts = <RP1_INT_DMA IRQ_TYPE_LEVEL_HIGH>;
clocks = <&sdhci_core &rp1_clocks RP1_CLK_SYS>;
clocks = <&rp1_clocks RP1_CLK_DMA &rp1_clocks RP1_CLK_SYS>;
clock-names = "core-clk", "cfgr-clk";

#dma-cells = <1>;
Expand Down Expand Up @@ -1226,18 +1231,6 @@
clock-output-names = "xosc";
clock-frequency = <50000000>;
};
macb_pclk: macb_pclk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-output-names = "pclk";
clock-frequency = <200000000>;
};
macb_hclk: macb_hclk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-output-names = "hclk";
clock-frequency = <200000000>;
};
sdio_src: sdio_src {
// 400 MHz on FPGA. PLL sys VCO on asic
compatible = "fixed-clock";
Expand Down
72 changes: 32 additions & 40 deletions drivers/clk/clk-rp1.c
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Original file line number Diff line number Diff line change
Expand Up @@ -927,7 +927,8 @@ static void rp1_pll_divider_off(struct clk_hw *hw)
const struct rp1_pll_data *data = divider->data;

spin_lock(&clockman->regs_lock);
clockman_write(clockman, data->ctrl_reg, PLL_SEC_RST);
clockman_write(clockman, data->ctrl_reg,
clockman_read(clockman, data->ctrl_reg) | PLL_SEC_RST);
spin_unlock(&clockman->regs_lock);
}

Expand Down Expand Up @@ -1503,8 +1504,6 @@ static const struct clk_ops rp1_varsrc_ops = {
.round_rate = rp1_varsrc_round_rate,
};

static bool rp1_clk_is_claimed(const char *name);

static struct clk_hw *rp1_register_pll_core(struct rp1_clockman *clockman,
const void *data)
{
Expand All @@ -1520,7 +1519,7 @@ static struct clk_hw *rp1_register_pll_core(struct rp1_clockman *clockman,
init.num_parents = 1;
init.name = pll_core_data->name;
init.ops = &rp1_pll_core_ops;
init.flags = pll_core_data->flags | CLK_IGNORE_UNUSED | CLK_IS_CRITICAL;
init.flags = pll_core_data->flags | CLK_IS_CRITICAL;

pll_core = kzalloc(sizeof(*pll_core), GFP_KERNEL);
if (!pll_core)
Expand Down Expand Up @@ -1553,7 +1552,7 @@ static struct clk_hw *rp1_register_pll(struct rp1_clockman *clockman,
init.num_parents = 1;
init.name = pll_data->name;
init.ops = &rp1_pll_ops;
init.flags = pll_data->flags | CLK_IGNORE_UNUSED | CLK_IS_CRITICAL;
init.flags = pll_data->flags;

pll = kzalloc(sizeof(*pll), GFP_KERNEL);
if (!pll)
Expand Down Expand Up @@ -1587,7 +1586,7 @@ static struct clk_hw *rp1_register_pll_ph(struct rp1_clockman *clockman,
init.num_parents = 1;
init.name = ph_data->name;
init.ops = &rp1_pll_ph_ops;
init.flags = ph_data->flags | CLK_IGNORE_UNUSED;
init.flags = ph_data->flags;

ph = kzalloc(sizeof(*ph), GFP_KERNEL);
if (!ph)
Expand Down Expand Up @@ -1620,7 +1619,7 @@ static struct clk_hw *rp1_register_pll_divider(struct rp1_clockman *clockman,
init.num_parents = 1;
init.name = divider_data->name;
init.ops = &rp1_pll_divider_ops;
init.flags = divider_data->flags | CLK_IGNORE_UNUSED;
init.flags = divider_data->flags;

divider = devm_kzalloc(clockman->dev, sizeof(*divider), GFP_KERNEL);
if (!divider)
Expand All @@ -1634,11 +1633,6 @@ static struct clk_hw *rp1_register_pll_divider(struct rp1_clockman *clockman,
divider->div.hw.init = &init;
divider->div.table = pll_sec_div_table;

if (!rp1_clk_is_claimed(divider_data->source_pll))
init.flags |= CLK_IS_CRITICAL;
if (!rp1_clk_is_claimed(divider_data->name))
divider->div.flags |= CLK_IS_CRITICAL;

divider->clockman = clockman;
divider->data = divider_data;

Expand Down Expand Up @@ -1668,7 +1662,7 @@ static struct clk_hw *rp1_register_clock(struct rp1_clockman *clockman,
init.num_parents =
clock_data->num_std_parents + clock_data->num_aux_parents;
init.name = clock_data->name;
init.flags = clock_data->flags | CLK_IGNORE_UNUSED;
init.flags = clock_data->flags;
init.ops = &rp1_clk_ops;

clock = devm_kzalloc(clockman->dev, sizeof(*clock), GFP_KERNEL);
Expand Down Expand Up @@ -1698,7 +1692,6 @@ static struct clk_hw *rp1_register_varsrc(struct rp1_clockman *clockman,
init.parent_names = &ref_clock;
init.num_parents = 1;
init.name = name;
init.flags = CLK_IGNORE_UNUSED;
init.ops = &rp1_varsrc_ops;

clock = devm_kzalloc(clockman->dev, sizeof(*clock), GFP_KERNEL);
Expand Down Expand Up @@ -1860,6 +1853,8 @@ static const struct rp1_clk_desc clk_desc_array[] = {
.max_freq = 200 * MHz,
.fc0_src = FC_NUM(0, 4),
.clk_src_mask = 0x3,
/* Always enabled in hardware */
.flags = CLK_IS_CRITICAL,
),

[RP1_CLK_SLOW_SYS] = REGISTER_CLK(
Expand All @@ -1874,6 +1869,29 @@ static const struct rp1_clk_desc clk_desc_array[] = {
.max_freq = 50 * MHz,
.fc0_src = FC_NUM(1, 4),
.clk_src_mask = 0x1,
/* Always enabled in hardware */
.flags = CLK_IS_CRITICAL,
),

[RP1_CLK_DMA] = REGISTER_CLK(
.name = "clk_dma",
.parents = {"pll_sys_pri_ph",
"pll_video",
"xosc",
"clksrc_gp0",
"clksrc_gp1",
"clksrc_gp2",
"clksrc_gp3",
"clksrc_gp4",
"clksrc_gp5"},
.num_std_parents = 0,
.num_aux_parents = 9,
.ctrl_reg = CLK_DMA_CTRL,
.div_int_reg = CLK_DMA_DIV_INT,
.sel_reg = CLK_DMA_SEL,
.div_int_max = DIV_INT_8BIT_MAX,
.max_freq = 100 * MHz,
.fc0_src = FC_NUM(2, 2),
),

[RP1_CLK_UART] = REGISTER_CLK(
Expand Down Expand Up @@ -2393,24 +2411,6 @@ static const struct rp1_clk_desc clk_desc_array[] = {
[RP1_CLK_MIPI1_DSI_BYTECLOCK] = REGISTER_VARSRC("clksrc_mipi1_dsi_byteclk"),
};

static bool rp1_clk_claimed[ARRAY_SIZE(clk_desc_array)];

static bool rp1_clk_is_claimed(const char *name)
{
unsigned int i;

for (i = 0; i < ARRAY_SIZE(clk_desc_array); i++) {
if (clk_desc_array[i].data) {
const char *clk_name = *(const char **)(clk_desc_array[i].data);

if (!strcmp(name, clk_name))
return rp1_clk_claimed[i];
}
}

return false;
}

static int rp1_clk_probe(struct platform_device *pdev)
{
const struct rp1_clk_desc *desc;
Expand All @@ -2421,7 +2421,6 @@ static int rp1_clk_probe(struct platform_device *pdev)
const size_t asize = ARRAY_SIZE(clk_desc_array);
u32 chip_id, platform;
unsigned int i;
u32 clk_id;
int ret;

clockman = devm_kzalloc(dev, struct_size(clockman, onecell.hws, asize),
Expand All @@ -2438,13 +2437,6 @@ static int rp1_clk_probe(struct platform_device *pdev)
if (IS_ERR(clockman->regs))
return PTR_ERR(clockman->regs);

memset(rp1_clk_claimed, 0, sizeof(rp1_clk_claimed));
for (i = 0;
!of_property_read_u32_index(pdev->dev.of_node, "claim-clocks",
i, &clk_id);
i++)
rp1_clk_claimed[clk_id] = true;

platform_set_drvdata(pdev, clockman);

clockman->onecell.num = asize;
Expand Down
12 changes: 12 additions & 0 deletions drivers/net/ethernet/cadence/macb_main.c
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Original file line number Diff line number Diff line change
Expand Up @@ -5023,6 +5023,17 @@ static const struct macb_config versal_config = {
.usrio = &macb_default_usrio,
};

static const struct macb_config raspberrypi_rp1_config = {
.caps = MACB_CAPS_GIGABIT_MODE_AVAILABLE | MACB_CAPS_CLK_HW_CHG |
MACB_CAPS_JUMBO |
MACB_CAPS_GEM_HAS_PTP,
.dma_burst_length = 16,
.clk_init = macb_clk_init,
.init = macb_init,
.usrio = &macb_default_usrio,
.jumbo_max_len = 10240,
};

static const struct of_device_id macb_dt_ids[] = {
{ .compatible = "cdns,at91sam9260-macb", .data = &at91sam9260_config },
{ .compatible = "cdns,macb" },
Expand All @@ -5043,6 +5054,7 @@ static const struct of_device_id macb_dt_ids[] = {
{ .compatible = "microchip,mpfs-macb", .data = &mpfs_config },
{ .compatible = "microchip,sama7g5-gem", .data = &sama7g5_gem_config },
{ .compatible = "microchip,sama7g5-emac", .data = &sama7g5_emac_config },
{ .compatible = "raspberrypi,rp1-gem", .data = &raspberrypi_rp1_config },
{ .compatible = "xlnx,zynqmp-gem", .data = &zynqmp_config},
{ .compatible = "xlnx,zynq-gem", .data = &zynq_config },
{ .compatible = "xlnx,versal-gem", .data = &versal_config},
Expand Down